Abstract: Graph neural networks (GNNs) have recently exploded in popularity thanks to their broad applicability to ubiquitous graph‐related problems such as quantum chemistry, drug discovery, and high energy physics. However, meeting demand for novel GNN models and fast inference simultaneously is challenging because of the gap between the difficulty in developing efficient FPGA accelerators and the rapid pace of the creation of new GNN models. Prior art focuses on the acceleration of specific classes of GNNs but lacks the generality to work across existing models or to extend to new and emerging GNN models. In this work, we propose a generic GNN acceleration framework using High‐Level Synthesis (HLS), named GenGNN, with two‐fold goals. First, we aim to deliver ultra‐fast GNN inference without any graph pre‐processing for real‐time requirements. Second, we aim to support a diverse set of GNN models with the extensibility to flexibly adapt to new models. The framework features an optimized message‐passing structure applicable to all models, combined with a rich library of model‐specific components. We verify our implementation on‐board on the Xilinx Alveo U50 FPGA and observe a speed‐up of up to 25x against CPU (6226R) baseline and 13x against GPU (A6000) baseline.

Bio: Cong (Callie) Hao is an assistant professor in ECE at Georgia Tech, where she currently holds the Sutterfield Family Early Career Professorship. She was a postdoctoral fellow in ECE at Georgia Tech from 2020-2021 and also worked as a postdoctoral researcher in ECE at the University of Illinois at Urbana-Champaign from 2018-2020. She received the Ph.D. degree in Electrical Engineering from Waseda University in 2017, and the M.S. and B.S. degrees in Computer Science and Engineering from Shanghai Jiao Tong University. Her primary research interests lie in the joint area of efficient hardware design and machine learning algorithms, as well as reconfigurable and high-efficiency computing and electronic design automation.