Beginning at the 130 nm node, copper (Cu) interconnection layers were introduced to replace conventional Al layers in order to reduce the wiring resistance in logic devices. Due to the inability to form volatile etch products at temperatures less than 180 °C, the damascene process has been the prevailing patterning technology for Cu. Continuous device scaling introduces additional challenges to the currently used damascene process. For example, the “size effect” of Cu is a phenomenon in which the electrical resistivity of Cu increases rapidly as lateral dimensions are reduced below 100 nm. This limitation could be overcome in part by the use of copper films with larger grain size. Although this change could be implemented by annealing sputtered or evaporated Cu films, this approach to film pattering requires a plasma etch step which has not been feasible to date. In this presentation we discuss a simple, hydrogen (H2) plasma-based, low temperature etch process that was developed to allow an alternative method to Cu damascene technology. The effect of various gases and plasma conditions on the etch anisotropy were studied and the combined effects of ion bombardment, ultraviolet photon impingement, and H interaction with Cu surfaces appears to be responsible for the efficient removal of Cu in low temperature H2-based plasma environments.

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